Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes successively more non-planar. This occurs because the distance between the outer surface and the underlying substrate is greatest in regions of the substrate where the least etching has occurred, and least in regions where the greatest etching has occurred. With a single patterned underlying layer, this non-planar surface comprises a series of peaks and valleys wherein the distance between the highest peak and the lowest valley may be the order of 7000 to 10,000 Angstroms. With multiple patterned underlying layers, the height difference between the peaks and valleys becomes even more severe, and can reach several microns.
This non-planar outer surface presents a problem for the integrated circuit manufacturer. If the outer surface is non-planar, then photo lithographic techniques used to pattern photoresist layers might not be suitable, as a non-planar surface can prevent proper focusing of the photolithography apparatus. Therefore, there is a need to periodically planarize this substrate surface to provide a planar layer surface. Planarization, in effect, polishes away a non-planar, outer surface, whether conductive, semiconductive, or insulative, to form a relatively flat, smooth surface. Following planarization, additional layers may be deposited on the outer surface to form interconnect lines between features, or the outer surface may be etched to form vias to lower features.
Chemical mechanical polishing is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head, with the surface of the substrate to be polished exposed. The substrate is then placed against a rotating polishing pad. In addition, the carrier head may rotate to provide additional motion between the substrate and polishing surface. Further, a polishing slurry, including an abrasive and at least one chemically-reactive agent, may be spread on the polishing pad to provide an abrasive chemical solution at the interface between the pad and substrate.
Important factors in the chemical mechanical polishing process are: the finish (roughness) and flatness (lack of large scale topography) of the substrate surface, and the polishing rate. Inadequate flatness and finish can produce substrate defects. The polishing rate sets the time needed to polish a layer. Thus, it sets the maximum throughput of the polishing apparatus.
Each polishing pad provides a surface, which, in combination with the specific slurry mixture, can provide specific polishing characteristics. Thus, for any material being polished, the pad and slurry combination is theoretically capable of providing a specified finish and flatness on the polished surface. The pad and slurry combination can provide this finish and flatness in a specified polishing time. Additional factors, such as the relative speed between the substrate and pad, and the force pressing the substrate against the pad, affect the polishing rate, finish and flatness.
One of the problems encountered as a result of chemical mechanical polishing of semiconductor wafers is the collection of residue on the edges of the semiconductor wafers. In particular, residue readily collects on the rounded edges of a semiconductor wafer during a chemical mechanical polishing operation. In chemical mechanical operations, for example, in which tungsten (W) plugs are formed and W etchback steps are performed, W residue collects on the edges of the semiconductor wafer.
Due to the W material character, organic materials and water are easily attracted, resulting in the collection of W on the wafer surface. Such a situation generally can induce a very poor adhesion between IMD layers and passivation film. Subsequent alloy and polymide coating steps, including curing thereof, typically generate a very strong tensile stress, which tends to pull up the passivation and causes wafer edge polymide bubble formation and/or polymide peeling. This can in turn contaminate the pad area and follow-up packaging processes. Both conditions tend to deteriorate the reliability performance of the resulting semiconductor wafer devices.
Based on the foregoing, the present inventors have thus concluded that a need exists for a method and system which will reduce and/or eliminate wafer residue collected on a semiconductor wafer as a result of chemical mechanical polishing.